Modern optical communications over single-mode fibers employ polarization multiplex (polmux) to double the spectral efficiency. After linear opto-electrical conversion, a “coherent” receiver de-multiplexes the polarizations and mitigates the relevant transmission impairments by digital means. Recently, both single-carrier and multi-carrier polmux transmission have drawn the interest of the optical community.
A prerequisite for correct processing at the receiver is correct symbol timing acquisition. This invention focuses on symbol timing synchronization for single-carrier coherent polmux receivers employing linear modulation.
Symbol timing recovery consists in estimating and correcting the frequency difference and the relative jitter of transmit and receive symbol clocks. In a high-speed system this is a critical task because the frequency components of the timing jitter extend into the high-frequency region. Tracking and compensating them poses challenging requirements for the bandwidth of the timing recovery circuitry.
In an optical coherent receiver accurate knowledge of the transmit symbol timing is a prerequisite for many processing tasks. Whereas a rough compensation of the bulk chromatic compensation can be performed before symbol timing synchronization, receiver tasks as adaptive equalization of PMD and residual CD, compensation of the carrier phase noise, and detection of the transmit data are conveniently performed after symbol timing acquisition.
The receiver depicted in FIG. 1 uses an adaptive Multiple Input Multiple Output (MIMO) equalizer to compensate residual CD and PMD. It estimates the timing error after the MIMO equalizer and corrects the sampling frequency before it. This architecture guarantees that the adaptive equalizer works with a synchronously sampled signal and, at the same time, that the timing error detector receives a clean signal after compensation of PMD and residual CD. Unfortunately, this solution requires the implementation of a long feedback loop embedding a component (the MIMO equalizer) that has a high latency. The long loop delay limits the bandwidth of the clock recovery and, therefore, its ability to track fast jitter.
On the contrary, the architecture illustrated in FIG. 2 is free of feedback loops and can potentially attain a high tolerance to timing jitter. However, it exposes the symbol timing recovery to a large portion of the signal impairments. As a consequence, the symbol timing recovery must be capable of extracting the timing information from a signal impaired by PMD and residual CD. The invention addresses the challenge of developing a robust timing phase estimator that can be used in the feed-forward architecture of FIG. 2.
A symbol timing recovery capable of tolerating PMD has been proposed in the patent application EP2375603. However, the described method and arrangement rely upon a feedback architecture (a phase-locked loop). The limited speed of digital electronics limits the loop bandwidth and thus the jitter tolerance. Consequently, this solution may not be suited for high-speed communications.